The architecture of Nyxx is designed to emulate the behavior of a real NES (Nintendo Entertainment System) at the hardware level. It is divided into three primary units: the CPU/APU, the System Bus, and the PPU.

Each of these components is implemented using explicit and minimal Zig structs to reflect actual hardware registers and memory maps as closely as possible.

CPU / APU

At the core of Nyxx is the 6502 CPU emulator, which handles instruction decoding, memory access, stack operations, and interrupt logic.

The APU subsystem is fully implemented, including memory-mapped registers, pulse channels, and audio output.

Nyxx now produces faithful 8-bit sound alongside video, completing the core NES experience.

The CPU interacts with all system components via a centralized Bus interface, mimicking the way a real 6502 processor accesses NES hardware.

• CPU registers like A, X, Y, PC, and the status flags are defined as fields in a Registers struct.
• Each instruction is emulated via discrete implementations with cycle-accurate behavior.

System Bus

The System Bus acts as the communication layer between the CPU and memory-mapped devices. It routes read and write requests to the appropriate target based on address decoding, including RAM, PPU registers, cartridge ROM, and more.

• Implemented as a Bus struct with routing logic in the read() and write() functions.
• Handles address mirroring and PPU register mapping, including $2000–$2007 and $8000–$FFFF for PRG-ROM.

PPU and VRAM

The PPU (Picture Processing Unit) is responsible for rendering graphics, managing background tiles, sprites, and the display frame buffer.